Resistive switching in ALD metal-oxides with engineered interfaces

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The key impact of incorporated Al2O3barrier layer on W-based ReRAM switching performance

In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO2 as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al2O3 layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al2O3 acts as an oxygen scavenging blocking layer at W sides, results in the filament path constriction at the Al2O3/HfO2 interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al2O3/HfO2/Pt to switch at 10 times lower operating current of 100 μA and 2 times higher memory window compared to the W/HfO2/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the Poole-Frenkel model

The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance

In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO2 as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al2O3 layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al2O3 acts as an oxygen scavenging blocking layer at W sides, results in the filament path constriction at the Al2O3/HfO2 interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al2O3/HfO2/Pt to switch at 10 times lower operating current of 100 mu A and 2 times higher memory window compared to the W/HfO2/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the Poole-Frenkel model

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. Although it has been proven that ReRAMs can memorize multibit information by the storage of multiple internal resistance states, the precise control of the multistates, their nonvolatility, and the cycle-to-cycle reliability are still open challenges. In this study, the analog resistance modulation of Pt/HfO2/Ti/TiN devices is obtained and studied in response to different programming stimuli, linking the electrical response to the internal dynamics of the ReRAM cells. The resistance modulation during RESET operation is explained by the progressive dissolution of the conducting filament, whose switching kinetics is inspected in detail, describing the filament evolution during voltage sweep measurements and under the effect of 1 mu s pulses. Exploiting the gradual nature of the RESET process, which is an intrinsic property of our devices, a linear resistance modulation over the wide operating window of 10(3) is obtained by negative pulse ramping. The intermediate resistance states are characterized by small spatial and temporal variability and stable retention over time. To explore the synaptic long-term plasticity properties, the resistance variation over 10(2) consecutive depression-potentiation cycles is presented and up to 15 discrete distinguishable states are defined through the evaluation of the maximum step-to-step variability. The linear resistance modulation over a wide resistance window coupled with the stable retention of intermediate states represents a fundamental step forward to enhance HfO2 ReRAM performance in neuromorphic applications

Switching Kinetics Control of W-Based ReRAM Cells in Transient Operation by Interface Engineering

Tungsten (W) is one of the most promising materials to be used in resistive random-access memory electrodes due to its low work function and compatibility with semiconductors, which raises the possibility of device integration, scalability, and low power consumption. However, W has multiple oxidation states that affect device reliability, due to the formation of semistable oxides at the switching interface. W chemical interaction is modulated through the insertion of Al2O3 or Ti interfacial layers. The time-dependent switching kinetics are investigated in transient Set/Reset operations. It is observed that a compact and stoichiometric atomic-layer-deposited Al2O3 barrier layer completely prevents W oxidation, resulting in a sharp current transient. The use of a sputtered Ti buffer layer allows a partial W oxidation, defining a tunable high-resistance state by pulse rise time control. Notable improvements in endurance, power consumption, resistance state stabilization, and cycle-to-cycle and device-to-device variability are reported. Switching kinetics and conductive nanofilament evolution are studied in detail to understand the microscopic effect of the interface modifications. The tunability of multi-HRS states by pulse timing control in Pt/HfO2/Ti/W is in the interest of network and brain-inspired computing applications, adding a degree of freedom in the modulation of its resistance

Tests of SEU effects of circuits developed in 130 nm CMOS technology

Two circuits have been studied for Single Event Upset (SEU) effects: ToPix4 (Torino Pixel) and the GBLD (GigaBit Laser Driver). The first one is the 4th generation custom prototype developed for the readout of the silicon pixel devices for the Micro Vertex Detector [1] of the PANDA [2] experiment. INFN, specifically the Sezione of Torino, is the leader of the development of this ASIC. The second one is part of the GBT project developed at CERN for the data transmission on optical links. It controls the laser diode that drives the optical fiber. INFN Torino department is involved in the design of this specific chip. Both ASICS are developed in a 130 nm CMOS technology and SEU protection techniques are applied to the digital parts

Environmental and economic assessment of lactic acid production from glycerol using cascade bio- and chemocatalysis

ISSN:1754-5692ISSN:1754-570

Resistive Switching in Sub-micrometric ZnO polycrystalline Films

Resistive switching (RS) devices are considered as the most promising alternative to conventional random access memories. They interestingly offer effective properties in terms of device scalability, low power-consumption, fast read/write operations, high endurance and state retention. Moreover, neuromorphic circuits and synapse-like devices are envisaged with RS modeled as memristors, opening the route toward beyond-Von Neumann computing architectures and intelligent systems. This work investigates how the RS properties of zinc oxide thin films are related to both sputtering deposition process and device configuration, i.e. valence change memory and electrochemical metallization memory (ECM). Different devices, with an oxide thickness ranging from 50-250 nm, are fabricated and deeply characterized. The electrical characterization evidences that, differently from typical nanoscale amorphous oxides employed for resistive RAMs (HfO x, WO x, etc), sub-micrometric thicknesses of polycrystalline ZnO layers with ECM configuration are needed to achieve the most reliable devices. The obtained results are deeply discussed, correlating the RS mechanism to material nanostructure

Multi-ReRAM synapses for artificial neural network training

Metal-oxide-based resistive memory devices (ReRAM) are being actively researched as synaptic elements of neuromorphic co-processors for training deep neural networks (DNNs). However, device-level non-idealities are posing significant challenges. In this work we present a multi-ReRAM-based synaptic architecture with a counter-based arbitration scheme that shows significant promise. We present a 32x2 crossbar array comprising Pt/HfO2/Ti/TiN-based ReRAM devices with multi-level storage capability and bidirectional conductance response. We study the device characteristics in detail and model the conductance response. We show through simulations that an in-situ trained DNN with a multi-ReRAM synaptic architecture can perform handwritten digit classification task with high accuracies, only 2% lower than software simulations using floating point precision, despite the stochasticity, nonlinearity and large conductance change granularity associated with the devices. Moreover, we show that a network can achieve accuracies > 80% even with just binary ReRAM devices with this architecture